Study And Design Of Current-mode Beidou Satellite Navigation System RF Front-end Circuits

Global Satellite Navigation positioning system has a wide application for military andcivil use, such as traffic navigation, time service, geological prospecting, geographicalmapping and so on. In order to strengthen national defense security and break up themonopoly of American and Europe in the field of satellite navigation positioning, China isstriving to develop Beidou satellite navigation positioning industry. Because theradio-frequency (RF) signal of satellite positioning is based on low power radiation spreadspectrum technology, it is giving rise to a harsh requirement for receiver sensitivity, signal tonoise ratio, image rejection and power restriction. In order to improve the portability andminiaturization of receiver equipment, it is becoming a research focus to realize the singlechip integration for Beidou navigation receiver.In this thesis, a current mode RF front-end receiver chip for Beidou navigationapplication was proposed, which consists of current-mode low noise amplifier and mixer,image-rejection filter, IQ synthesizer and low pass filter. Firstly, a new topology ofcurrent-mode low noise amplifier (LNA) circuit was proposed. The propsed LNA usescapacitive cross-couple technology to achieve significant improvement in noise figureperformance. In addition, the LNA also has the function of single-ended to differential-ended,which can replace the traditional balun. This ability can help improve the conversion gain andcommon mode noise rejection. A new mixer was also proposed. The proposed mixer usesswitching current mirror technology and thus can achieve high conversion gain. Also, itreuses the bias current of the LNA, therefore can reduce the power consumption. Othertechniques such as I,Q orthogonal topology and third-order multi-phase filter circuit structurewere also used in the design of the RF front-end to achieve high image rejection rate.Finally, the current mode RF front-end chip circuit was implemented and verified withGlobal foundry180nm CMOS process. Post-layout-simulation results show that the currentmode low noise amplifier and mixer with a supply voltage of1.2V and a RF signal frequencyof1561.087MHz can obtain an NF of3.5dB, an input P1-dBof-30dBm, a conversion gain of43dB, an image rejection ratio of49dB and a power consumption of10.8mW. The low passfilter can provide out-of-band rejection ratio more than40dB with supply voltage1.8V. Thepower consumption of the whole RF front-end circuit is12.6mW. The chip layout area is0.75×0.97mm2. It is demonstrated that the designed RF front-end chip can meet the harshrequirements for advanced Beidou receiver system.