The Design Of Current Mode RF Receiver Front End

The demand of low cost, low power and small size circuits has been increasing with extensive researches on transceivers architecture and RF circuit design, especially in Bluetooth and802.11WLAN areas. Furthermore, LNA, mixer, oscillator are the essential building blocks of modern communication systems. For a conventional voltage mode LNA and mixer, The LNA input FET converts the incoming signal into current, which then becomes a voltage across the load. This voltage drives the transconductance input of the mixer, which once again converts the signal into current. Finally, the mixer differential pairs commutate this current, translating it in frequency, to be read off at the mixer output as voltage. We can see, the I-V (traditional LNA output) and V-I (Gilbert mixer input) conversion are unnecessary.Voltage mode circuits operate with high impedance nodes such that voltage swings are large. Here, we propose a current mode RF front end processing of current signal. Current mode approach has some advantages, such as extended bandwith, ease of addition, subtraction and multiplication of signals, simple circuit structure, higher dynamic range, suitability of operation in reduced power supply environment, low power consumption, low voltage Operation, micro-miniaturization.In this paper we have designed the current mode LNA and mixer integrally as a whole. It contains a differential transconductance low noise amplifier(GBmB-LNA) and a differential current-mode down converted mixer. The single-terminal of the Gm-LNA just contains one MOS transistor, two capacitors and two inductors. The gate-source shunt capacitors make the gate inductance LBgl,2B to be chosen very small value. The current-mode mixer is composed by four switched current mirrors. Adjusting the ratio of the drain channel sizes of the switched current mirrors can increase the gain of the mixer, and increase the gain of RF receiver front-end accordingly. This RF front-end operates under Ⅳ supply voltage. The receiver RFIC was fabricated in a chartered0.18μm CMOS process. The integrated RF receiver front-end has a measured power conversion gain of17.48dB, an input referred third-order intercept point (IIP3) of-7.02dBm. The total noise figure is4.5dB and the power is only14mW. This work doesn’t need the I-V and V-I conversion used in conventional LNA and mixer coupled by voltage. Compared to folded LNA and mixer, the gain of this work is bigger. Compared to the LNA and mixer coupled by current mirror, voltage supply of this work is lower.The development of single-chip RF circuits is desirable to enable implementations at low cost. The full integration of transceivers implies the use of low intermediate frequency (IF) or zero-IF architectures that require quadrature local oscillator (LO) signals for image rejection and demodulation. The quadratre oscillator, in this work, uses the superharmonic capacitor coupling method. It has the advantage that no extra noise sources and power consumption are introduced to the circuit in the coupling process. What’s more, the coupling capacitor is easy to be implemented in RF integrated circuit with small die area. To get low supply voltage, coupled oscillators are folded. The folded-type quadrature LC oscillator has achieved excellent noise performance. The phase noise offset100kHz from the carrier is-94.14dBc/Hz and only-122.9dBc/Hz offset1MHz from the carrier. The circuit draws only7.4mA from a0.8-V supply for applications requiring low phase noise and low supply voltage.