Research On Transmit-receive Circuit And The Key Techniques Of Phased Array Ultrasonic Technology

As the fast developing of modern industry, many kinds of equipment and material are becoming muchmore complex than before, whose working environment also has been changed, and presenting newrequirements to non-destructive testing. Depending on the unique characteristic and superiority,Ultrasonic phased array is becoming to take on more testing duty than before, gradually to take overan important place in non-destructive testing, and become the hot spot of research. This is theinevitable trend to the development of non-destructive testing.This paper has completed the design of ultrasonic phased array device, solved thehighfrequencyproblemto transmit-receive circuit, raised the resolution of phased array time delay, and theprototype can work collect in crack testing. The research content is presented below.The design methods of high speed digital logic was researched, a high delay resolution circuit ofphased array which is based on a single low cost FPGA chip was designed and completed. Accordingthe characteristic of the FPGA which was used, a design method based on PLL about time delaycircuit was presented. While combining the integrity, the time delay resolution has achieved1ns bythe design whose input clock is just50MHz. To bring about the intelligence and high efficiency, asystem on chip was designed by NIOS II processer, who can reshuffle the device parameters withoutreboot.This research also has completed16channels circuit of phased array, overcame the problem of highfrequency and high voltage, picked up signal in mv level successful. Through selecting, testing andimproving different chips, the ultrasonic transmit circuit driven by ISL55110was made, who canmatch the high frequency and high voltage requirements. A diode bridge was designed beforediode-clamped, to solve the high frequency and high voltage problem, and kept useful signal in mvlevel. To interface the digital logic circuit, the line delay on PCB was limited to minimum by placing,line compensating, interface line designing, shielding and so on, to match the resolution of device.Above all, a16channels phased array prototype with high time delay resolution was designed, andworked correct in crack test to standard test block.