On-chip Memory Design For Test And Design For Debug

As the sizes of integrated circuit continue to shrink and the complexity graduallyincrease, the debug and test have become the urgent problems which need to beaddressed in the chip design.As the proportion of embedded memory in SoC has gradually increased, to detectthe defects and failures effectively in the embedded memory, a high-quality embeddedmemory test method must be designed, which can improve the overall yield and savethe cost of test and manufacturing. At the same time, the traditional memory testmethods can not locate and observe the failure in memory. To debug the errors in thedesign better, an efficient debug method must be designed.In this paper, the main contributions are as follows. First, a March YY algorithm isproposed. March YY is based on March algorithm which is widely used in the industry.With the analysis of the single unit fault and the coupled fault, the March elements thatsolve each fault are abstracted according the state transition diagram and then, theMarch C+algorithm is optimized according to the abstracted March elements. TheMarch YY algorithm inherits the advantages of the symmetrical structure in the MarchC+algorithm and the three failures of WDF, CFdsxwx and CFwd with the reasonablecomplexity. Second, MBIST controller based on the March YY algorithms is designed,implemented and simulated. Third, the original read and write logic circuits of MBIST,the macro test structure based on MBIST controller is designed and implemented.Results show that March YY algorithm can cover all of the simple type faults shownin this article, with the prospect of engineering application; MBIST circuit design whichbased on the algorithm has correct functions, with good theoretical reference value; themacro test structure based on MBIST controller reduces circuit overhead effectively andimplements the function of memory macro test,with a high practical value.