Design And Verification Of Programmable Digital Down Converter

In the radar system, the MF radar receiver take the responsibility to receivethe IF signal modulated. The signal imported is required to be transferred to lowsampling rate and low frequency that digital signal processer be able to process.As the most important part of radar receiver, digital down converter (DDC)realize the down convert function by decimating, filtering.In this paper, based on the theory of multi-rate signal processing, in order tosatisfy the requirement of frequency and sampling rate for MF radar receiver inradar system, improve the applicability and reusability, a structure includingnumerically controlled oscillator module with CORDIC arithmetic and8quarterquadrant mapping arithmetic, CIC filters, CIC compensation filter, and half-bandfilter for a programmable digital down converter is proposed. The aim is torealize the transform of signals’ down sampling rate ranging from1to16384. AMATLAB model is built to obtain the specifications of DDC, a fixed-pointconversion from floating point to fixed point is designed in order to consume lesshardware, and an imp lementation of RTL model is built based on that. Intendedto test the down convert function of DDC, an IF sig nal is imported into the modelbuilt, and the simulate result show that DDC model built before can realize thedown convert function that is demanded in radar system. At last, a system onchip based on the LEON3processer is designed and verified, which is able totransfer the continuous data from DDC to processer without any loss.