| The rapid development of information society has brought the huge amounts ofvideo information, and promotes the development of video compression technology.The current mainstream video compression standard is still the H.264. Peoplepursuit of high-definition video. High-definition video decoder need large datastorage requirements and frequent data reading and writing. The decoder bring a lotof hardware resource consumption and power consumption. It makes theperformance of the storage system limit the main bottleneck of decoder speed.In this paper, the the storage requirements of high-definition video decodingmodule are analyzed in detail. According to the storage needs of each functionalmodule, we design bitstream and stream buffer memory in bitstream parsing module.In intraframe prediction unit, we design the prediction mode and the adjacentreference block storage structure. In the interframe prediction unit, we designed themotion vector memory, and the reference block storage and hierarchical structure.In deblocking filter unit, we design the filter data storage and data control of itsstructure, and presents address generation mechanism of reconstruction images.The storage structure is designed by Verilog HDL and use the modelsim tool toverificate the decoder. We use JM18.5software decoder as the model of the decoderdata can be compared. After verify the decoding function correctly, we set the SoCverification platform, using Xilinx ML605board to do FPGA verification.Finally, we use the ISE software to synthesize decoder, and we find the highestworking frequency is71.136MHz. At the same time, we counted decoding cyclesof three groups of video sequences.The result shows that in the worst case, a singleframe decoding the longest cycle is2.35×106. And decoder can still meet therequirements of real-time decoding. |
