Software Design Of H.264 High-definition Video Decoder Based On MSC8144

Emerging applications like video over wireless channels and the increasing popularity of High Definition (HD) are requiring higher video quality and, at the same time, higher compression efficiency which H.264/AVC is capable to provide. In this paper, an implementation of H.264 high definition video decoder is presented. Based on MSC8144, the Smart OS calls 4 Cores, up to 1 GHz each, to parallel decode the high definition compressed bitstream with a resolution of 1920x1080, which is received from the host, and then the decoded video data is sent to display.Chapter 1 gives an overview of the background, including the principles of video compression, a short description of the exiting video coding standards and an introduction of the DSP development.Chapter 2 discusses the multicore architecture characteristics and applications of MSC8144 processor. It covers the core subsystem, memory hierarchy, cache and DMA data models, instruction set and the IDE CodeWarrior.Chapter 3 explains detailedly the H.264 video coding key techniques. The concept of NAL is defined. The intra prediction, motion compensation, integer transform, context adaptive entropy decoding and in-loop deblocking filtering are presented. In addition, different tool set for different Profile is described briefly.Chapter 4 is devoted to the most important part of this paper. System scheme and module design is given based on MSC8144. The software design of HD video decoder is focused. These include different modules: Smart OS scheduler, bitstream receiving, video data sending and decoding. Special interest is paid to interpolation process, deblocking filtering and entropy decoding, which are the kernels of decoder. Methods of improving the decoder are designed.Chapter 5 is the conclusion.