| As the development of the microarchitecture of a single core, the instruction levelparallelism (ILP) exploration is almost to the end. Now the exploration about the threadlevel parallelism (TLP) and the data level parallelism (DLP) has become the maindevelopment trends in the world. In order to explore the parallelism from differentlevels，this paper proposed Many–Thread wide Vector architecture which orientsscientific computing. This architecture can explore the ILP,TLP and DLP at the sametime.This paper has completed two main work which is modeling and analyzing aboutthe MTV architecture.First, this paper founded the function model and the performance model for theMTV architecture, and formed a full system simulator finally. In terms of functionmodeling,The MTV simulator founded the models of all kinds of registers,memorysystem and the procedure of the instruction executed. In terms of performance modeling,the MTV simulator founded a five stages out-order pipeline which supports manythreads architecture and the branch prediction. The MTV simulator adopted the rubymodule to simulate the memory system of MTV architecture to make the memorysubsystem research convenient. The ruby module was used in the gems simulator whichis adopted and accepted by the most architecture researchers. The MTV simulator usedthe modular design and dynamic-link technology to make the modules loadeddynamically, which improved the flexibility of the simulator. Meanwhile, the MTVsimulator used a parallel programming technology and instruction decoding cachetechnology, which significantly improved simulation speed.Second, this paper formed a profiling frame of the memory system on chip basedon the designed MTV simulator. this paper also made a preliminary study for the MTVarchitecture memory subsystem using the frame. Based on the analysis of experimentaldata,this paper proposed a memory subsystem improvement scheme to support scalarand vector access simultaneously, and did some analysis about this scheme. |
PDF Full Text Request