The Research And Implementation Of The Key Techniques On Single Chip Multiprocessors

Enhancing the performance of microprocessors is the uppermost goal of all researchers. The fast development of the semiconductor's technology provides a wide space for chip design. Currently one of the most important tasks of computer architecture's further advancement is how to make full use of the endless recourses of the on chip to implement faster and more efficient microprocessors with shorter time.There are many limitations of improving the microprocessor performance on traditional architectures by exploiting further ILP (Instruction Level Parallelism), such as the occasion, the scope, the self-architecture, the implementation of hardware and so on. Adopting on chip multithreading architectures and extracting TLP (Thread Level Parallelism) is an efficient way to conquer these limitations. SCMP (Single Chip Multi-Processors) can simplify the hardware implementations further when exploiting TLP. Running general-purpose applications on SCMP has the best research and application value. In order to improve the execution efficiency of SCMP for general-purpose applications, this paper studies the key techniques and gives the following contributions:1. This paper proposes a SCMP model, called SWT (SCMP With TLS), which supports TLS (Thread Level Speculation). Design principles of SCMP and characteristics of general-purpose applications are considered when designing the SWT architecture. TLS, an important way to simplify TLP extraction, is implemented in SWT naturally.2. This paper presents a thread partition algorithm that focuses on general-purpose applications. Many factors, which influence the execution efficiency of SCMP, are considered in this algorithm. Based on the CFG (Control Flow Graph), the algorithm evaluates thread size and inter-thread data dependence quantitatively by the profiling information. It sets up a partial order to analyze the program structure more efficiently. The hardware cost in TLP extraction is also referred when designing the heuristic principles in this algorithm. Only a few changes are made when adopting the algorithm on other multithreading architectures.3. This paper issues a method for maintaining data dependence based on a dual-ring structure. Inter thread data dependence is an inevitable problem on multithreading architectures. The quality of data dependence maintaining method affects the performance of processor directly. Based on SWT, we unite the data speculation of TLS and data dependence. A method for data dependence based on dual-ring structure is designed in these conditions. The method can be implemented with little design complexity. With this method, inter thread synchronizations can be eliminated and conflicts in maintaining data dependence operations are reduced in SWT.