Study On The Key Technologies Of Thread-Level Speculation On Multi-core Platform

Entering the 21st Century, with the development of integrated circuit technologies, the processor architecture have stepped into a time of multi-core since the constraint of power consumption and design complexity. However, the traditional. serial programming model and linear address space model have no essential change, a gap appeared between the parallel architecture and the serial computing model. Thread-Level Speculation (TLS) was proposed to fill this gap and made it possible to speedup the tradition serial program via multicore processor. But now, TLS was still in the stage of academic research and still have a long distance to practical use, and there are a lot of pivotal questions need to answer, so "Study on the Key Technologies of Thread-Level Speculation on Multi-core Platform" was selected as the title of this dissertation.In this dissertation, we have studied three facets of TLS: analysis and locating of TLS parallelism, TLS programming and code transformation, and TLS architecture support for chip multi-processor (CMP). (1) In the investigation of TLS parallelism's location and analysis, we proposed several criterions of judging whether a program is suitable for TLS, method and theory of how to locate TLS parallelism in a specified program, and we also designed and implemented a suit of profiling tools for TLS; (2) In the research of TLS programming and code transformation, we have implemented a base run-time system for speculative execution of loops and subroutines, which makes the speculative execution of loops and subroutine roboticized partly and simplified the programming of TLS greatly; (3) In the architecture research of CMP with TLS support, we checked the necessary hardware support for TLS, and proposed a base TLS architecture. (4) We have also implemented a behavior-level simulation platform for multicore processor, investigated the performance optimization of both hardware and software, and achieved design space searching of multi-core processor, acquired new cognition of several TLS pivotal question.This dissertation selects programs of SPEC CPU 2000 as case studies. On one hand, the investigation of TLS parallelism's location an analysis shows that: (1) there a lot of subroutines in the program, whose return value are predictable, and they take an execution time of exceed 50%, and the simple last-value return value prediction scheme is good enough. (2) Loops, whose granularity is too small, is more than that ones, whose granularity is too big, and loop chunking is necessary to control the granularity of TLS threads. (3) Data dependences are ubiquitous for both loop structure and subroutine structure, and the synchronization mechanism is necessary. (4) For the lack of TLS parallelism in program, the number of processors that TLS can effectively utilize is smaller than 4.On the other hand, the behavior simulation show that (1) Single bus connection can not bear the weight of the communication during speculative execution, bus splitting can alleviate this question, but when the number of processor exceed 4, multi-bus connection will become the bottleneck of the system. (2) Complex and wide-issue superscalar core is not necessary for building a CMP chip with TLS support, but out-order issue technology is necessary. (3) Compiling optimization is more significant than complex hardware effort, thread partition model and synchronization support are the most important factors for TLS.