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Design Of Data Acquisition And Transmission For Nano-CT System

Posted on:2015-10-02Degree:MasterType:Thesis
Country:ChinaCandidate:J YuanFull Text:PDF
GTID:2298330422472817Subject:Control Science and Engineering
Abstract/Summary:PDF Full Text Request
Based on the operational principle and system characteristic of nano CT, this paperproposes collection and transmission system plan due to the high density bedding faceCCD and designs the hardware and software for the system against the acquisition,processing and transmission problems of the huge amount of data.The overall solution of rapid data collection and transmission based on the kodakbedding face array density CCD KAF-16803is Determined.With the thought ofmodular design, this system is divided into detection acquisition module and datatransmission module. Using KAF–16803,Detection acquisition module completes theX-ray signal detection, and implemented by CCD special modulus conversion chipAD9824modulus conversion, the converted data stored by caching module; Datatransmission module by using the combined model of FPGA and PHY chip, completesthe network transmission of data, using Verilog HDL language to complete the datapackage and transmission, and corresponding program compile, integration, simulation.Due to the overall scheme, detailed hardware design scheme is proposed. Throughanalysis, comparison and choice of the performance and characteristic of the CCD chip,the main control chip,the AD chip, the physical layer chip and the transmission mediumdetermining the basic hardware solutions.Then respectively introduced the hardwareimplementation of each module and the role of each unit circuit is presented, includingA/D conversion circuit, PHY chip circuit, FPGA chip peripheral circuit and powercircuit.Based on the hardware design,system software is designed, Emphasis on theimplementation of the logic system. The design of digital logic circuit uses the modulardesign method from the top down, completed the acquisition module of CCD KAF-16803and AD conversion chip AD9824sequential control, data cache and logicaldesign of the transmission module gigabit Ethernet UDP protocol. Using Verilog HDLlanguage in QuartusII9.1platform accomplish compile, integration, simulation.
Keywords/Search Tags:Nano-CT, Data acquisition and transmission, CCD, Gigabit ethernet, FPGA
PDF Full Text Request
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