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Research On FPGA Based Gigabit Ethernet Camera Transmission System

Posted on:2014-11-24Degree:MasterType:Thesis
Country:ChinaCandidate:G S ShenFull Text:PDF
GTID:2268330401465088Subject:Optical Engineering
Abstract/Summary:PDF Full Text Request
Optoelectronic image processing has great importance for manufacturingautomation equipment, artificial intelligence, automatic recognition and many otherfields. With the constant improvement of the requirements for the resolution of theimage recognition, image pixels are much higher than before which causes urgentrequirements of high bandwidth and fast processing ability to transmit and processingimages. In some circumstances which require multiple cameras to collect images at thesame time, the traditional means of transmission should adopt multiple graphicsacquisition card (or multiple computers). However, with the increase in the number ofthe camera, the costs of the transmission part will increase greatly.To solve the problems above, this dissertation sets transmission part of thedistributed image acquisition system as the main object of study. FPGA (FieldProgrammable Gate Array) based gigabit Ethernet camera transmission system wascarried on the thorough discussion and research.During the design process, reasonable division of the module is applied. The use ofthe top-down design pattern, the division of system function and the coordinate betweeneach module were detailed discussed. To improve the performance of the system, thecharacteristics of parallel structure of the programmable logic devices was fullyconsiderd. The code was designed with the consideration of portability on differentplatforms.The basic theory of UDP/IP protocol was discussed, then the dissertation discussedthe relevant function modules which involved in the transmission system, such as UDPsend module, UDP receiver module, ARP sending module, ARP receiver module, MACcache module, the send module of the MAC layer, the receiver module of the MAClayer, the physical layer control module, CRC generation module, CRC check module,etc. The system was designed based on FPGA and Verilog HDL, simulated by thesimulation tool Modelsim, implemented using the Quartus II development tool. Thedesign was downloaded to the DE2-115development board of Altera Corporation forvalidation and the transmission data was captured by the network data capture tool Wireshark to determine the validity of the design.
Keywords/Search Tags:Gigabit Ethernet, UDP/IP, FPGA, image transmission
PDF Full Text Request
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