Hardware Design And Implementation Of High Speed On-board Camera Compression System

Space camera is widely used, as chinese space industry develops rapidly, With the constant improvement of the performance of space camera, the image quality of space camera become higher and higher. Large amount of high-quality image data will be produced in a short period of time. Thus, it is necessary to produce a kind of compress system to reduce the amount of data to be storaged and the transmission time of image. In addition, in order to fit the camera’s high speed interface, the design of a reliable high-speed data acquisition unit has become the difficulty point.Based on the actual needs of XX- 2 space lab project, high speed on-board camera compression system has realized the design of image compression, high-speed interface and large capacity data storage that mentioned above. The system has passed a variety of function test and performance test, and has been applied to the space program successfully.Xilinx company’s FPGA with a model of XC5VLX110 is selected as the core control device. With the advantage of rich RAM and FFT resources, virtex- 5 series FPGA is possible to realize a high complexity and high performance system design. As a coding device of JPEG2000, ADV212 can benefit from the enhanced quality and features provided by the JPEG2000 image compression standard. DDR SDRAM is selected as the high-speed image cache device, and FLASH as the core storage device with a large capacity.This system has realized the dynamic configuration of detector via the SPI bus, and the acquisition of parallel high-speed image data outputs by the detector through LVDS in use of IDELAY and ISERDES. After cached by high-speed DDR SDRAM, a frame of image data is compressed by the compression chip of ADV212 using the standard of JPEG2000. In order to meet tasks in different environment, FPGA is used to configure the compression mode of ADV212 in the process of compression. Compressed code stream and image data with out compression are cached by FLASH memory with large capacity. Thanks to the nonvolatile characteristecs of FLASH, the system is powered down when the camera is free in order to reduce power consumption. Finally package of corresponding compression code is sent to the earth accroding to the download instructions. After the system design is complete, construct the ground test platform to sumulate the process of camera imaging, image processing, and data transmission. Strict function test and performance test have been done upon each module to ensure that timing of interface, speed, and data accuracy meet the design requirements.This article first introduces the JPEG2000 compression standard upon the content and advantages, and the characteristics of the ADV212 compression chip. After that the requirements of function and performance besides the system structure of the high speed on-board camera compression system are introduced. Then the whole system is divided into individual modules according to the difference of function, after which the specific design of each module is introduced in detail. Finally, the function test and performance test of the whole system is illustrated in detail.