Research On Method Of Reliability Evaluation Based On C6000 Instruction Set

With the rapid development of space and satellite technologies and the application requirements for Very Large Scale Integrated circuit(VLSI), the dependence on DSP and other integrated chips grows deeply. On the other hand, with the microprocessor design goals turning to low power and high performance, the trend of small-scale circuit design and the reduction of supply voltage make the microprocessor affected by Single event upset(SEU) more severely, and soft error occurs more frequently. As for the running of aerospace devices, the existence of any error may lead to a great disaster. The soft error rate reflects the possibility of failure or damage. Therefore, the evaluation of soft error should be an important issue to be considered in the design.In view of the DSP microprocessor Single event upset causes the phenomenon of soft error easily. In order to reduce the soft error rate and the cost for the overall protection,targeted protection need to be done. Based on C6000 series chip as the research object, this paper studies the vulnerability evaluation method, and analyzes the key problems need to be solved in the study. Finally, the proposed evaluation method has carried on the experimental test. The main work can be summarized as follows:(1) The thesis proposes an evaluation method applied to DSP C6000 instruction set. The research starts at static assembly instructions. Based on whether the output on the application program affected by Single event upset effects to evaluate soft error rate. Through the analysis of the assessment indicators, makes the soft error rate evaluation turn to vulnerability evaluation, and notes the key issues should to be addressed in the evaluation.(2) The thesis analyzes the current research status, and points out the advantages and disadvantages of the current evaluation methods. Based on the close relationship between the soft error rate and application, and the lack of the current research on the application of reliability evaluation method, according to the study of the architecture vulnerability indicators, the vulnerability evaluation method is proposed for the application. And the calculation model is also analyzed.(3) During the evaluation process, the paper classifies the instruction based on the output of the instruction, then traverses the assembler instructions and identifies each type instruction. The dynamic dead instruction can be identified by establishing the instruction list and operands consumer- producer chain. The collection of the Un-ACE and ACE-bits are competed based on the binary instruction word. Then the evaluation can be realized by combing with the calculation model. The method avoids the complexity and huge costs that cone from repeated injection and large number of simulations.(4) In the evaluation method of DSP, different from the conventional fault injection, the method needn’t understanding of the structure of the microprocessor completely. And through analyzing the instruction set, the application can be divided into some modules according to certain rules. It is analyzed in each module. In order to reduce error rates and resource overhead comes from protection, the module whose error rate is high should be protected.Through the multiple sets of experimental evaluation, the method is proved to be viable. The proposed evaluation method is aimed at instruction set. It isn’t limited to the specific architecture. And in the experiment, because of the simple operation and short cycles, the efficiency greatly improved. So it maybe applied widely.