The Modeling And Verification Of Single-Event Upsets In Transistor Circuit

Charged particles in the space radiation environment have significant influence on the performance and lifetime of the flying spacecraft in space. With the increasingly widely application of integrated circuits, electronic equipment in spacecraft is more and more susceptible to interference by the charged particles in space. Further studies and evaluations need to be carried out as failures caused by single event upset(SEU) cannot be ignored. Currently, methods to assess the effect of single event upset include space experiments, ground tests and computer simulation. It is necessary to conduct a simulation study on SEU as such method is easy and quick, and space experiments and ground tests require high costs and take a long time to finish.The paper introduces the history and status quo of studies on SEU, analyzes its mechanism and discusses research directions and methods of SEU. It made a brief introduction of the simulation software used. Modeling and simulation are used to research the SEU of bulk silicon devices, which help determine the factors that affect SEU. Simulation results showed that the higher the working voltage of a bulk silicon device, the stronger the anti-SEU. The device is more prone to upset with a high linear energy transfer coefficient in charged particles. The longer the effective path of injection of heavy ions into the sensitive areas of the device, the easier the device upsets. The ISE-TCAD software is employed to conduct modeling and simulation of SOI-based devices, and analyze and compare the anti-SEU of bulk silicon devices and SOI-based devices under different factors. Results indicated that the anti-SEU of SOI-based devices has greatly improved compared with that of bulk silicon devices.