Design And Study Of VCO For PLL Application

A detail analysis about the phase noise of voltage controlled oscillator (VCO) ismade in this paper based on the basic principle of VCO. According to the analysissome methods are put forward to reduce the phase noise of the voltage controlledoscillator based on1μm GaAs heterojunction bipolar transistor (HBT) process, a fullyintegrated LC voltage controlled oscillator used in phase lock loop（PLL）frequencysynthesizer with low phase noise is designed and implemented. A feedback π–networkand a common-emitter transistor configuration are employed in the LC VCO. Largefiltering capacitance is used to reduce phase noise. Simulation，layout design andpost-simulation are completed by1μm GaAs HBT process. The chip size is0.7mm×0.7mm. Chip testing results show that the frequency of the LC VCO can betuned from23.57GHz to23.85GHz. In the center oscillation frequency, the phase noiseof the LC VCO can achieve-93.76dBc/Hz at1MHz offset. The maximum output poweris about-1.49dBm and the dc power consumption is104mW.The basic principle of the PLL which consists of a phase detector, a loop filter, aVCO, and a dynamic frequency divider is presented in this paper. The simulation resultshows that only when the reference frequency is9.45GHz to9.52GHz could the PLLbe locked. The locking time is100ns, and loop bandwidth is400MHz, phase margin is54°. Finally, the testing results have been analyzed.