The Design And Implementation Of Rs Encoder And Decoder For Loran-C Roadbed Navigation System Based On FPGA

Loran-C navigation system is mainly used in military field, the reliability of the information transmitted in the channel is an urgent problem to be solved, because of its strong error correction capability, RS code has been widely used in storage media, telecommunications, computer, digital television and network to enhance data reliability. According to ITU-R M589.3, RS (30,10) code is a standard subgrade code for Loran-C navigation system. Based on the characteristics of the communication channel in Loran-C navigation system, an RS codecis designed and implemented in this article to meet the demands of Loran-C system, all the computation are based on GF (27).The main contents of this thesis are as follows:1. Overveiw the research status and significance of Loran-C system, RS codecs and FPGA in this thesis.2. The division operation is equivalent to multiplication in the Galois Field, the design of a finite field multiplier is proposed in this thesis, and a two-stage optimization is applied for the finite field multiplier, to improve coding efficiency and reduce hardware resources.3. The design of a general RS(30,10) encoder is completed in this thesis. Since continuous coding cannot be realized in a general RS encoder, a continuous encoderis designed and implementedbased on the general encoder to meet the real-time requirements of the Loran-C navigation system.4. The RS(30,10) decoder is completed in this thesis.The design and implementation of the syndrome calculation module, BMA module, Forney module and Cheinearch module are realized by Verilog hardware description language and are simulated in the software QuartusⅡ. Moreover, the correctness of the design is verified by Matlab.5. The RTL simulation and the FPGA implementation of the improved continuous encoder and decoder is,completed in this thesis.QuartusII ISE9.1and Modelsim simulation platform development tools are used in this thesis. The codes arewritten in verilog language and appropriate testsare carried out in Modelsim. Then the tests results are compared with those outputed by Matlab, to show the correctness of the continuous encoder and decoder designed in this thesis.The portability of the RS encoder and decoder designed in this paper is strong, and can be applied to other communication channelsafter some modifications, so it has a certainresearch and application value.