Digital If Simulation Of Radar Reference Signal Based On FPGA

With the rapid development of modern radar technology, radar systems not only play a very important role in the civilian, such as navigation and mapping; but also occupy an important position in military applications except the war. However, in practical application, the test radar systems, particularly the test of the transmitted signal, if only use the external field in testing, it will put a lot of expenses in manpower, material and other aspects. With the environmental conditions uncontrollable, it greatly increased the difficulty of debugging. So it is the trend to analog transmission signals which is high repeatability and which can improve the simulated radar performance under the same conditions. It can easily to analysis and docking well enough shorten the work cycle. Therefore, It is necessary to analog reference signal in a wide variety of radar.This paper presents a FPGA digital IF analog reference signal based on radar, the frequency to a baseband digital signal in the frequency band for digital simulation of the radar system so that the actual condition does not have the front end, a rear stage of the radar system for debugging. Articles explain in detail the structural principle of the whole system, a common way to generate a reference signal radar and radar reference signal. And on this basis, the key modules of the reference signal generated by the radar is analyzed. Subject developed radar reference signal is divided into four blocks:a baseband signal generation module, the digital up-conversion processing module, converter module and the interface module. Synchronous clock circuit and synchronous reset design, timing reference signal by various PRF control while explaining the direct digital frequency synthesis (DDS) technology, digital upconversion technology, digital down conversion technologies, double data rate memory technology and other key technologies.This paper uses the algorithm verification and circuit simulation combination, using Verilog HDL hardware design and implementation of programming languages to complete the hardware circuit. Combined with EDA software Modelsim10.0for circuit simulation and synthesis, FPGA chip achieve a functional and performance verification on Quartus Ⅱ, and through the oscilloscope displays the results in Fig. Commissioning results show that the design of the circuit to be completed by the subject of bandwidth600MHz, IF1.2GHz,3.6GHz high-frequency design requirements, but also to complete the triangle wave, sawtooth wave, point-frequency analog signals such as chirp radar signals in an FPGA chip the realization of the digital simulation of the entire radar frequency reference signal.