Circuit Design, Dsp And Fpga-based Radar Signal Sorting

Deinterleaving of radar pulses, is a very important part of modern electronic countermeasures. With modern electronic technology, Field Programmable Gate Array (FPGA) is more and more popular with electronic designer. Also, the performance of Data Signal Processor (DSP) has improved. This paper presents a radar signal deinterleaving circuitry using DSP and FPGA.The article focuses on the algorithm for radar signal sorting. Cumulated difference histogram (CDIF) and sequence difference histogram (SDIF) are used when sorting radar signals. In order to compare these two algorithms, this paper simulates sorting of radar signals with these algorithms. Based on the advantage of sequence difference histogram, this article improved the accumulated difference histogram algorithm and give out a circuitry depending on this algorithm. The contributions of this thesis are shown as following.Firstly, design a circuitry including FPGA, DSP, the external memory, power supply and other external circuit.Secondly, write VHDL program. With this program, the FPGA can fulfill the corresponding logic circuit. FPGA can collect the time information of rising edge and falling edge during a specific time.Finally, DSP processes the information that is collected by FPGA. DSP gives out the pulse repetition intervals (PRIs ) of different radar signals. The host processor updates the library of radar signals depending on the result of the deinterleaving of radar signals.