Font Size: a A A

Design Of Cache Based On16Bit High Performance CPU

Posted on:2015-01-28Degree:MasterType:Thesis
Country:ChinaCandidate:Q WenFull Text:PDF
GTID:2268330428966816Subject:Information and Communication Engineering
Abstract/Summary:PDF Full Text Request
With the development of microelectronic, semiconductor manufacture and computerscience technology, the performance of CPU and Memory is improved constantly. Theimprovement of memory speed falls behind of the increase of CPU speed. This gapimpacts the improvement of CPU performance. Cache technology is critical for solvingspeed matching between CPU and Memory; this paper carries out investigation onCache accordingly.Instruction-Cache module is based on high performance CPU DMT251core whichis developed by Datang Microelectronic Technology Corporation. The design is tooptimize performance of DMT251core. This CPU uses three class pipeline frameworkand its instruction collection have strong function. It mainly deals with16bit instructionand is also compatible of8bit,24bit,32bit instruction. This core can be applied onvarious IC card. Because DMT251core can deal with non-constant length instruction,this lead to boundary problem accrued on Cache design comparing with constant lengthCache. It is difficulty and critical technologic of the design.First of all, the article review the development of Cache technology, summarizeresearch status of Cache, important transform and key innovation. Secondly, tointroduce Cache theory and IC design method. Lastly, this design chooses4KB CacheSRAM and direct-mapping mode, completes Cache frame, work flow, address mappingand state machine. The article adopts top-down IC design method and usesVerilog-HDL to complete RTL code design of instruction Cache function. Cachemodule chooses the mode of fetching instruction directly from flash to solve boundaryproblem caused by non-constant length instruction.Finally, simulation of module level and system level is executed. Instruction Cachesystem achieve design requirement from simulation waveform. The paper also analyzesresult of Cache,Ibuf and fetching instruction from flash about performance of thetheory and contrast of simulation. It indicates that instruction Cache improves systemperformance evidently on running long time program and achieves prospective purposeof engineer design.
Keywords/Search Tags:Cache, 16bit CPU, direct mapping, non-constant length instruction, Verilog-HDL
PDF Full Text Request
Related items