Research On ISA Mapping Of Co-design X86Emulation

Emulation technology could effectively relieve the problem of software compatibilitycaused by architecture difference. It is very important to the development of RISC CPUsespecially for domestic CPUs’. Nowadays, X86CPU has occupied a larger of market share andowned extensive software resources. In the case, domestic CPUs have to provide compatibilityfor software based on X86platform so that they could be accepted by users and obtain themarket share. Co-design X86Emulation involves both the advantages of software and hardwareso that it could obtain a better performance of X86Emulation than other realizations. Thus,Co-design X86Emulation has become one of the directions for X86Emulation developments.After investigating the state-of–the-art X86Emulation technologies and analyzing theperformance bottlenecks of X86Emulation, we discuss the key issues in ISA mapping ofCo-design of X86Emulation and design Instruction Translation Unit and Translation Cache Unit.The main contributes of this thesis are as follows:To solve the problem caused by uncertain length and variable format of X86Instructions,we propose a two-stage decoding mechanism. The two-stage decoding mechanism divides thedecoding process into length decoding and operand decoding which could reduce the cycle costeffectively. According to the micro-program designed in Pentium and micro-operation designedin QEMU, we design a Trans_lib based on LUT which is accessed by address entrance andfunction entrance. The Trans_lib convert the instruction translation to table walking which couldreduce the time and power cost. We propose a hardware translation cache management HTCM.The Translation Cache is divided into hot codes and common codes, which are managed byFIFO and Full-Flush. HTCM could reduce the cache pieces and extend the survival time of hotcodes. Finally, we achieve the two hardware unit using Verilog HDL and describe the main portsand their functions.Verification and experiments showed that the Instruction Translation Unit and TranslationCache Unit could correctly complete the ISA mapping from X86to Alpha. And the cycle cost oftwo-stage decoding mechanism reduced up to15.79%compared to decoding by Byte. The hitrate of HTCM improved up to9.27%and17.43%compared to Full-Flush and FIFO.