Parallel Compile Analysis Of Ladder Diagram And It’s Implementation On FPGA Platform

The Programmable Logic Controllers(PLCs) has been widely used for complex control ofindustrial machinery.Ladder diagram (LD) is the most popular programming language ofPLCs.Higher speed and precision is the persistent pursuit of PLCs.Since heart of PLCs ismicrocontroller(MCU) which follow von neumann structure,to accelerate it’s response performancemeans to reduce the scan cycle.Adopting CPUs with higher processing speed is an availablemethod,but still CPU’s frequency bottleneck will turn up.More positive and effective way is topromote the program’s execut pattern.Combine the ideas of GPU and the concurrent executioncharacteristic of very high-speed hardware design language(VHDL) together,developing a new typeof pure hardware of PLC control system(hardware PLC)which execute parallel rungs concurrently.is a feasible method.Studied papers about PLC’s parallel compilation, LD/Petri net to logic circuittransformation,refer to the part of the theoretical basis, the subject put forward a kind of parallelinstruction execution implementation scheme of PLC, The specific design content includes thefollowing:(1)Put forward the overall plan of LD to VHDL, such as building in a VHDL framework likethree-stage control scanning mechanism; abstract LD into logical expression, each expressioncorresponds to a single output cascade, design algorithm to implement set logical expression toVHDL code conversion.(2)Analyze the LD as a whole. Discuss its dependencies and decomposition method, so as toestablish LD concurrent execution model, and lay a foundation for parallel PLC.(3)Analysis of LD locally. Reference directed graph theory, abstract each cascade into AOVdiagram, design special algorithm to implement AOV graph to Boolean logic expressions, getpreliminary logical expression of each cascade, all steps of logical expression and its locationinformation constitute the complete logic expression of LD.(4)Implement the LD instruction set on the hardware of PLC.According to the enforcementmechanism of differences LD instruction set is divided into the following four categories: processcontrol instruction (jump instruction, etc.), basic instruction (set/reset instruction, etc.), commonlyused instructions (timer, counter, etc.), function instructions (transfer instructions, thearithmetic/logic operations, etc.), and explain the different VHDL design method of all kinds ofinstructions.(5)Establish LD to VHDL into grammar rules library, lexical rules library. The combination of above five parts can obtain corresponding LD control program, the VHDLprograms downloaded to the FPGA chip, the pure hardware logic can be realized in the hardware ofPLC.LD’s parallel compilation and hardware logic implementation issues, both at home and abroadhas not been mature design. Instruction parallel execution of PLC system, is still in the primaryexploring stage, has a large distance from the commercial application。The subject put forward akind of implementation methods which based on VHDL language and hardware PLC of parallelinstructions, hope it has certain reference value for further research,in related field.