The Research Of Converting Ladder Diagram Into VHDL Logic Expression

IEC61131-3standard defines two types of programming languages: textualprogramming language and graphical programming language. Ladder Diagram(LD)programming language is one of the most popular graphical programming language. Since theheart of a PLC(Programmable Logic Control) is a sequential processor, its performancedepends on the speed of the microcontroller entirely which limits the performance of the PLCgreatly. PLC will lose its advantage gradually in industry especially in the ultra-fast,ultra-precision and high reliability control field.In order to enhance the performance of conventional PLC, the paper presents a new PLCdesign base on the FPGA(Field-Programmable Gate Array) with reconfigurable hardwarearchitecture and execution mechanism. Since LD is the most popular programming languages,the core of this paper is to convert LD into its equivalent high speed hardware descriptionlanguage VHDL(Very-High-Speed Integrated Circuit Hardware Description Language) whichis the main programming language in FPGA. In order to convert the ladder diagram withcomplicated function modular and multi-output rungs into VHDL program, logic expressionwhich based on AOV(Activity on Vertex) diagram is adopted as a bridge to reduce thedifference between them. The thesis proposed a new algorithm which based on the methodof backward inference in splitting a multi-output rung. Not only simplifies the process ofrung splitting, the algorithm but also can improve the performance of splitting significantly. Adetailed analysis of the dependence relashionship is done in the paper for the complicatedladder diagram. By converting control dependencies,ladder diagrams with JMP and CALLinstructions can be translated into VHDL program successfully. In addition, in order tosimplify the translation process of a imcomplete rung, an algoritm named layer repairing andtranslation algorithm is proposed. A imcomplete rung will be repaired by the layer repairingalgorithm and a complete one will be translated into VHDL logic expressions perfectly by thetranslation algorithm. For a complete rung, the out-degree of a branch node must be equal tothe in-degree of the corresponding merging node while imcomplete one has no suchcharacteristic.In order to verify the correctness of algorithms proposed in the thesis, an applicationwhich can dectct the relay jitter frequency as well as the jitter time interval accurately is done.Experimental results show that algorithm proposed in the paper is correct.