The Study Of Embedded System For Image Enhancement Processing And Its Realizing

Image enhancement is mainly to converts the image to be more suitable to observe by human eye or analysis and identification by machine, improve image quality and visual effects in order to obtain an image with more clear and useful information. For aerial images, the poor weather conditions and shooting distance will lead to the image with low contrast, blurred texture detail.The harsh weather conditions cause some problems such as:low contrast of the aerial image, missing details. In this paper we propose an algorithm of brightness preserving histogram specification with maximum entropy in each dynamic sub-layer to enhance aerial image. In this method, firstly the histogram is divided into four sub-layers equally,and then according to the probability density distribution,we will re-map gray value range of sub-layers to complete the expansion of the dynamic range, thereby increased the contrast of the image. In order to enhance the image details better, we maximize entropy under the constraint of constant brightness in each sub-layer.In order to enhance the image in real time, we designed the embedded system for image enhancement processing. Through the research programs about functional requirements、the overall structure of the hardware and system software architecture, finally we designed parallel system composed of multi-processor FPGA and DSP. We discussed the key technologies involved in this system, including Camera Link interface technology, high-speed digital signal processor (DSP) technology, large-scale field programmable logic array (FPGA) technology, and ASI interface technology. On the basis of requirement of the actual project, we select the suitable main chip of system. In this system the Altera’s Cyclone3series chip EP3C16Q240FPGA were selected as coprocessor for caching data in the system and all digital logic control, TI’s TMS320C6455DSP chip as the main processor in the system to complete the image enhancement processing. About the software of system, Verilog HDL hardware description language was used to design functional modules of the FPGA, including image acquisition module, image cache module and image transmission module. In this system dual-port RAM of the FPGA were used as high-speed cache, and by using the ping-pong operation to accomplish the buffer of high-speed real-time image data. This mechanism ensured coordination of DSP and FPGA parallel work. By using EMIF interface of DSP to read cached image data in the cache memory FPGA in EDMA manner and then DSP will accomplish enhancement processing, and finally processed image data via the EMIF interface of DSP in the way of EDMA transferred back to the FPGA, FPGA received the data from the DSP in accordance with the ping-pong operation. Finally the FPGA according to ASI interface protocol for transmission processing data to subordinate systems.Through the system hardware and software combination debugging, this system can complete1024*1024*8bit*30frame image enhancement processing per second.