Design Of Analog Circuits And Layout For Sensor SOC

Sensor SoC needs to work in various environments. Thus, the analog part which is the most directly connected with the external world,not only needing to consider the circuit function and reliability which meets the application requirements, but also needing to design a circuit with higher performance and cost-effictive.The thesis is aimed at researching on the technologies of power management, ADC and DAC. An LDO which realizes regulator from3.3V to1.8V and I/O circuit are designed; An8-bit R-2R DAC is designed; A10-bit SAR ADC according to segmented capacitor array DAC and latch-up comparator is design;The layout design verification of DRC/LVS is completed.The following are the key technological problems solved in this thesis:1) In the LDO design, the LDO’s poles are moved to high frequency by adding a buffer, and the LDO is able to work stably under various loads by adopting large capacitance compensation.2) In the DAC design, the resistance matching difficulty decreases thanks to the voltage-mode R-2R array structure. Meanwhile, an MOS switch is used to reduce the influence of the matching error.3) In the SAR ADC design, the offset voltage of comparator is reduced by using pre-amplify latch-up comparator. The chip size and the power consumption are decreased by using segmented capacitor array DAC structure.The thesis adopts the standard CMOS technology to complete the analog circuits with the standard CMOS. The simulation results show that the LDO’s temperature coefficient is less than5ppm/℃ranging from-40℃to85℃. DAC is8-bit with30MHz. Meanwhile, the SAR ADC is10-bit, and the sample rate is100kHz.