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Decoding And Digital Audio Stream Information Technology Research Series

Posted on:2015-03-14Degree:MasterType:Thesis
Country:ChinaCandidate:L S MaFull Text:PDF
GTID:2268330425987712Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Broadcast Studio Center program sends out a signal of AES/EBU standard audio stream signals and transmitted to each radio transmitting station via satellite. In the radio transmitting stations, a wrong operation by mistake the port may cause a wrong program sends. The paper design a monitoring system based on the signal of AES/EBU standard user information bits by inserting identification code in the source signal to achieve multi-channel Identification and monitoring of the program signal, the system also provides RF signals monitor.The paper expatiates the data structure of the AES/EBU standard audio stream signal at first, describes the effect of each information bit in the signal and put forward the plan which based on inserted a identification code into the user information bits. Next, designs the hardware part of the system, the system module is divided into four parts, they are the top-level core board with ARM microprocessor, the bottom core board with connecting modules and the encoding and decoding board with FPGA. The main function of the system is that the control board sents the identification code to the encoding board via the SPI and inserts the code into the user information bits on the encoding board, then the signal is transmitted to the decoding board, decoded the signal and pick up the identification code from the user information bits, the code is sented to the control board and shown on the screen. The system provides the function of the audio monitoring.The paper describes the encoding and decoding process of the AES/EBU standard audio stream signal in detail. The system uses the FPGA chip of EP1C3T144C8which made by the Alter Company for the AES signal codec work. The system achieves the communications of the SPI and the I2S, the L3port contral for the chip of the UDA1341ts, and shows the simulation results for some module.Finally, the paper shows the results and analysis of the system operation, compared the expected functional and the actual operating results, then dishes some problems in the subject and makes a certain outlook on future work.
Keywords/Search Tags:AES/EBU standard, FPGA, UDA1341ts, codec, I2S, L3
PDF Full Text Request
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