Design Of HD Video Codec Circuit

With the development of the society, image stitching technology has become more and more widespread, especially in the areas of military, medical, etc. Due to the limitation of camera equipment can not shoot the big picture, image stitching technology is a good solution. This technology use a series of small spatial perspective images by computer matching, then spliced into an ultra-wide image without slit viewing. The mosaic image perspective is bigger than traditional image.This paper designed the decoded hardware circuit of the image stitching technology. eight-way video input, and six of which have 1920x1080 resolution with 30Hz refresh rate HD SDI video, two-way is 720x576 resolution with 25Hz PAL B/W analog video. Finally, output a 1920x1080 resolution with 25Hz refresh rate HD SDI video. The output video requires continuous, clear, no flickering and screen continuous smooth.This paper describes a high-definition video codec circuit design. Firstly, HD SDI signal processed by the equalization, decoding the signal from the serial data to the parallel data. Then through the stitching conversion, the parallel data was processed to the serial data by coding. Finally output the video signal which was required. In order to realize the reception and output of HD/SD video signal, the system hardware circuit is consist of GS1524 equalizer, GS1561 decoder, GS1532 encoder, GS1528 drive, GS1525 clock, AD AT89C2051 and SAA7113H converter, power supply and memory system. Master controller used the Altera’s Cyclone VE Series FPGA chip 5CEFA7F31. Describes the overall framework and the whole process of hardware selection of this system, and debugging it.