The Desigh And Research Of Routing Algorithm And Simulation Model On Network On Chips

As the growing development of semiconductor technology and integrated circuits, more and more IP cores integrated on one single chip. Some problems have become difficult to be solved in designing SoC based on chip bus. Firstly, synchronization of global clock is impossible. Secondly, address space is limited. Thirdly, chip bus can not support multi-node parallel communications. Lastly, the bus system is not flexible enough to be expanded. The quantity of IP cores and system performance are restricted due to the problems above. As a consequence, the technology of computer networks was transplanted into SoC design to solve systematic problems of chip bus and this has been the hot topic in research field. At present most of researches about NoC focused on topology structure, router and routing algorithm.The main works of this thesis focused on the aspects of above. This thesis mainly introduced the common NoC topology, and the popular routine techniques and algorithms. At the same time, a XY-YX Routing algorithm of a 2D mesh structure is presented, which is based on researching the turn model. The algorithm is deterministic, minimal and deadlock-free. Proof of deadlock freedom is presented. Finally, the algorithm is simulated on 4×4 2D Mesh topology network to evaluate and analyzed the performance through NIGAM experiment platform.In order to valuate the feasibility and practicability of the NoC structure, we designed efficient hardware emulation and testing platform primarily consisted of DSP and FPGA. Furthermore, we proposed a NoC routing node based on 2D Torus topology, wormhole Exchange mechanism, E-cube routing algorithm, GALS structure and virtual channels. After that, we gave functional definition of the router module, design and verification programs, data packet format definitions, sub-modules division scheme and circuit details. And then we analyzed the routing node, which lay the foundation for future research on NoC.