Research On Image Processing Hardware Library Based Reconfigurable System

The general-purpose microprocessors have the advantage of short development cycle and high flexibility, however, the processing efficiency is low for the reason of serial-executed instructions and translation. In contrast, with a high degree of parallelism, ASIC (Application Specific Integrated Circuit) is customized and optimized for one specific kind of applications, which leads to high processing speed. But the bottleneck is the long developing cycle and high production cost. A compromise between the two main processors is made by the reconfigurable system, which consists of controllable hardware. It has high processing efficiency and flexibility at the same time, which leads to rapid development.In this paper, reconfigurable computing system architecture is researched. An image processing system is designed, which is coarse grained and static reconfigurable. A three-layer architecture is employed, which is composed of configuring, connecting and processing library layers. Circuit-switched transferring with faster communicating speed is inserted into each router node which is used to connect processing modules with standard interfaces for image processing system. The mapping and routing algorithm between hardware library and connecting layer is also designed. All the elements are implemented with HDL and synthesized. The result shows that a reduction of10%LUTs and15%registers is achieved.