Hardware Implementation Of Real-time Image Enhancement And Display System Based On Multicore DSP

Real-time transmission and processing of image data increasingly become a hottopic in many areas. In the field of optical detection, in order to improve thecapability of target tracking of the equipment, a variety of high-performance imagesensors are widely used in the front-end of the optical collection system, whichmakes the electronic system of image acquisition and processing of the back-endfaces greater amount of image data, so the system needs higher data transferbandwidth and more powerful data processing capabilities. Meanwhile, with thedevelopment of image enhancement algorithms, the selection of bosom system chipshould also take full account of the requirements of the complexity of the algorithm.Through the selection of high-performance bosom components and the design of thehigh-speed serial bus, the original intention of this study is to solve data transferbottlenecks and processing bottlenecks currently faced image acquisition platform.High-performance multicore DSP+FPGA architecture is capable of powerful dataprocessing and flexibility, and the data flow structure designed by the custom fiberoptic protocols, SRIO and PCI-e implements efficiency and reliability from the datainput all the way up to the output. This makes the new system have the capability tomeet the application requirements of the current image acquisition and processing.Firstly, on the basis of application requirements analysis, this paper put forwarda basic structure of the new generation of image enhancement and display system.Next, through the comparison and the analyze of performance parameters of avariety of high-performance DSPs and FPGAs, I pick up the bosom chips of thesystem, and implement a peripheral circuits design in consider of the multi-core DSPand FPGA power consumption, the clock demand and the external storagerequirements. Selection of high-performance chips accomplished in the highcapability of data processing of the system, and in the basis of bosom processor, thedata transmission capacity is achieved through the selection of high-speed serialbuses. Then the article presents data flow structure of the system, describes the basiccontent and specific implementations of the custom fiber protocol, SRIO and PCI-e.After the completion of the system design, the paper shows the high-speed PCBdesign of the system, through good layout and wiring to ensure the integrity ofsignal, and reduce the interference transmission of line effects. In the last state of hardware design, the paper indicating that the platform is well designed through thedisplay of debugging processes of the system power, the clock, and the varioushigh-speed interface clock. Finally, based on the accomplishment of debugging, thepaper put a haze removal algorithm to run on the DSP, the result showed a goodeffect of haze removal and a relatively high efficiency of the algorithm.This paper completed the hardware design and the basic debugging of a newgeneration of system applied for image enhancement and display, and effectivelyachieved the real-time image data processing capabilities and high bus bandwidthrequirements, which is practical in engineering.