Research On Fault-Tolerance Techniques Against Single Event Effects For SRAM-based FPGAs

SRAM-based FPGAs are gradually applied to the field of aerospace as low cost, highdensity, etc. However, the SRAM-based FPGAs are volatile memory and susceptible to singleevent effects. A lot of work about detection and reinforcement of single event effects onFPGAs has been done oversea, and a variety of FPGAs test reports on FPGAs have beengenerated. At present, domestic reserch focuses on single event effects detection of FPGAs.Therefore, this thesis presents the basic structure and working principle of FPGA and studiesSRAM-based FPGAs single event effects, especially single event upsets on FPGAs. A seriesof studies for existing SEU mitigation techniques have been launched. The main work andinnovations of the thesis are listed as follows:Firstly, since the conventional TMR design of fault-tolerant systems are subject tomajority voting unit (Voter), Xilinx XTMR method has been studied in the thesis. The XTMRmethod can ensure that the output results are correct when SEU occurs on any path of thetriple modular redundancy.Secondly, the thesis researches the reinforcement method suitable for BRAM based onboth TMR and EDAC and introduces reinforcement design for memories with arbitrary databit width by using the Hamming code, and RM(2,5) code to correct multiple bit upsets. Onthe other hand, consideing the EDAC module has no ability of anti-radiation; the thesisprompts EDAC triple modular redundancy reinforcement design.Thirdly, the Virtex-4devices have readback and dynamic reconfiguration features, thethesis studies its configuration process in-depth, the configuration principle and thetechnologies of scrubbing and readback used in fault-tolerant design.Fourthly, some circuits and units with fault tolerance capability have been designedbased on the existing fault-tolerant design methods. Shift register and UART with triplemodular redundancy are implemented. Synthesis constraints and Hamming-3code are usedrespectively to design security state machine. The fault-tolerant asynchronous serialtransceiver IP core is designed with EDAC and TMR methods. The fault injection simulationhas been done for the IP core, the simulation result show that it meets the designrequirements.Finally, the thesis gives fault-tolerant circuit design reinforcement strategies byanalyzing the Single Event Effects on FPGAs, for the system reliability and performancerequirements from the actual engineering projects.