Research On Data-driven Crosspoint-Queued On Chip Router

There are many challenges in multicore era such as parallel programming, multicorecommunication and memory hierarchy. Above all, parallel programming is severely limited bythe architecture of control flow computer (von Neumann computer) which is generally used inrecently multi-core processor by serial executive mode in essence. Secondly, it is the challengethat the more cores integrated, the more power consumption and interconnect delay are multicorecommunication needs to face with. So, it is an important subject to solve. Finally, memoryhierarchy is faced with the ’cache coherency’ in CC-NUMA, which leads to the problems ofcommunication more and more seriously.For the issues above, data flow computer and networks on chip are consideredsynchronously with the innovative idea that cache hierarchy and interconnect must be studiedtogether, whose key issues lie in low-latency communication network and toleration of largecommunication delay for data-driven strategy. So the data-driven crosspoint-queued (CQ)on-chip router is proposed including data driven module (DDM) and CQ on-chip router. Datadriven module implements the data-driven mechanism while CQ on-chip router is mainly usedfor communication.Firstly, the mathematical model of CQ router is built for simulation using matllab accordingto the M/M/1model of queuing theory in this thesis. The results shows that when the queuedepth is four and using round rbin scheduling algorithm, the performance is excellent. And then,the RTL design of data-driven CQ on-chip router is finished including distributed CQ on-chiprouter and the lumped one based on the results of simulation. Finally, a full-custom distributedCQ on-chip router which has been proven to achieve better performance is implemented in45nmCMOS process of FreePDK. In the working condition that the temperature is700C and thevoltage is1.1V, the delay of critical path is0.271ns; the total power dissipation is267.5438mWand the layout area is0.0845μm2; meanwhile, the data-driven distributed on-chip router isverified in FPGA. The results show that it can achieve multi-core communication effectively with good scalability.