The Baseband Processing Unit Design Of High-speed Broadband Frequency Hopping System

Frequency hopping communication is a kind of spread spectrumcommunication technology, which is a hot topic in international research since itwas used in military in1980s. Frequency hopping communication has very wellanti-jamming performance and anti-interception capability, it is also easynetworking, so it is widely used in military and civilian fields.This paper focus on the key technology of CHESS system, SINCGARSsystem and JTIDS system based on the research situation of frequency hoppingsystem. But modern military communication system requires higher-speed datatransmission capacity and more reliable anti-interference ability. Based on theabove background, this paper studies the baseband processing unit design offrequency hopping communication and its FPGA realization,In the system project design, the baseband unit studies data frame mode，frequency hopping sequence design, frequency hopping synchronization, thebaseband signal uses FSK modulation and demodulation and such relatedprocessing unit. This project uses m-sequence, DDS hoppers, and uses digitalcorrelator and multi-phase sequence matched filter as the frequency hoppingsynchronization method. The baseband frequency hopping communicationsystem achieves10kHop/s hop frequency rate, after the sampling frequencyhopping synchronization completed, the timing error is reduced to1/10of onesymbol period.The system hardware platform design use FPGA as the core of operation andcontrol, including DDS, A/D, D/A and memory chips as the key module offrequency hopping communication system, complete the correspondingschematic design, and provides fully expandability to the access of the mixer andthe DDS.In the common hardware platform use FPGA as the core, has realized thebaseband processing and frequency hopping synchronization, gave the specificanalysis of the baseband data frame structure and frequency hoppingsynchronization through the analysis of each module’s simulation and thefunction test result of online logic analyzer, thus verified the synchronizationscheme of this paper is feasible.