Design And Implementation Of High-speed Frequency Hopping System Based On Dual Frequency Hopping Pattern Synchronization Method

With the increasing requirement of communication quality, the upgrading speed of communication technology is becoming faster and faster. Just not long after the commercial 4G,some technology related to 4G+ and Pre 5G has been put forward constantly. The development of communication technology inevitably makes the electromagnetic environment in space more and more complex, as well as brings more and more interference.However, frequency hopping communication has very good anti-interference, anti-fading,anti-interception and other characteristics, which makes it a good application in both military and civilian communication.This paper designed a high-speed FH communication system. Since the system's frequency hopping speed is as high as 10000hops/s,which makes the receiver is difficult to guarantee the carrier phase's correlation at the frequency hopping time,the non-coherent 2FSK modulation method was adopted. FH system's carrier frequency is changing constantly in the process of communication, which makes FH synchronization become a key part of FH system,so the article presented the design idea,the overall scheme and the implementation process of the system, with emphasis on research and design of the system 's synchronization scheme.Based on the study of general FH synchronization methods and combined with waiting type self-synchronization method and synchronization-head method, a dual frequency hopping pattern synchronization method was be designed to accelerate the speed of FH synchronization. Some designs in two aspects of FH capture and tracking have been done to reduce the FH synchronization time: First, the waiting type serial capture method was used for FH capture, but capture time of this method is associated with the cycle length of FH pattern. Hence, combined with synchronization head method, this thesis designed a new scheme, which used FH pattern of short period to transmit synchronization header information during synchronization and utilized FH pattern of long period to send data in the stage of data communication. And it could shorten the time of FH capture, meanwhile, the FH gain couldn't be affected during data transmission. Second, a tracking method based on FH clock signal was applied for FH tracking. In the process of its implementation, this article designed a multi-level sampling structure, which could reduce the error of FH clock between receiver and transmitter down to the level of several sampling points,and could complete the tracking process very fast.Finally, the Verilog HDL program of each module in system was written, and the designs of each part were simulated by Modelsim 10.1c. After that, the program was be downloaded to the FPGA hardware platform for testing the system, and verified the validity of the system designs.