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Low-power Field Programmable Analog Array Design And Application Research

Posted on:2014-01-15Degree:MasterType:Thesis
Country:ChinaCandidate:B LiuFull Text:PDF
GTID:2268330401990132Subject:Power electronics and electric drive
Abstract/Summary:PDF Full Text Request
Field Programmable Analog Array (FPAA), as a new kind of integrated circuit,appears in recent years. To achieve the desired circuit functions, the internalconnections and parameters of such devices can be changed by receiving the externalinput configuration data according to the actual needs, which is similar to the FieldProgrammable Gate Array (FPGA). With the advantages such as simplicity, flexibility,etc., FPAA has a wide application prospect in many fields of industrial automation,aerospace, neural network and so on.In integrated circuit design, it’s easy to design a digital circuit for its powerfuldigital chip and convenient development tool (called Electronic Design Automation,EDA), and only power consumption and speed need to be considered. While there is acompromise between power, speed, linearity, gain, signal swing, supply voltage andbandwidth in analog circuit design, in addition, the effects of noise also needs to beconsidered. For these reasons, it’s hard to design an analog circuit.The work on this paper focus on the design of a low-power field-programmableanalog array and its applications is prepared as follows:(1) The research background and significance of FPAA are introduced, and theresearch actuality and the further development are analyzed.(2) The principle and design method of FPAA are introduced, and take aclassification on the current implementation techniques.(3) Using CSMC0.5μm CMOS process, the FPAA’s sub-blocks are designed,including a differential digitally controlled linearly tunable OTA, a programmablecapacitance multiplier, a configurable analog block and a hexagonal interconnectionnetwork, and the performances of these circuits are confirmed through the PSPICEsimulation results.(4) The applications of the FPAA are explored, and their structure and principleare analyzed. To verify the functions of these application examples, PSPICEsimulations were done.(5) Based on the CSMC0.5μm CMOS process, the layouts of each major cellcircuits and a2×2array FPAA are finished.The research of this paper is funded by National Natural Science Foundation ofChina (61176032).
Keywords/Search Tags:FPAA, CAB, POTA, Capacitance multiplier, Hexagonal interconnectionnetwork topology
PDF Full Text Request
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