Software Radio Key Technology Research And FPGA Implementation

Software Defined Radio (SDR) has attracted worldwide attention of the wirelesscommunication field once the concept is proposed. It has become one hot topic in the fieldof radio communication. The basic idea is based on a common, standardized, modularhardware platform which can realize different application function through softwareprogramming. SDR has liberated the design from the method based on hardware.Channelized receiver with poly-phase filters is the core content. The full parallel andpipelined FFT is the key technology which can channel the detected signal. And it willgreatly reduce the response time of the channelized receiver. Thus, all the`containedinformation has been remained. DDC (Digital Down-Convert) technology is one keytechnology of SDR, which follows closely after AD sampler. The main function of DDC isextracting the digital data from broad-band data which is digitalized by AD sampler,down-converting interested spectrum to near zero frequency, and decreasing the samplingrate of the data effectively. Further processing will be done by general-purpose DSPprocessor.On the one hand, this dissertation deals with the FPGA implementation of full paralleland pipelined FFT technology. In this part, we have mainly completed the algorithmimplementation, algorithm optimization and design programming using Verilog HDLhardware description language. Taking radix-4and radix-8FFT algorithm for example, wehave finished the design of64points full parallel and pipelined FFT which can becompleted in only one clock cycle. Further, the64points full parallel and pipelined FFT isco-simulated in Modelsim and Matlab software. Results show that the FFT design in thisdissertation is perfect, the operation efficiency is greatly increased, a lot of hardwareresources are saved. At last, all the designs have been tested and verified on Xilinx Virtex5XC5VLX110T hardware platform.On the other hand, this dissertation deals with the FPGA implementation of DDCtechnology. In this part, we have made reasonable implementation scheme. The architecture of DDC is proposed by this dissertation, and each of the key modules in thesystem are analyzed in theoretical study and simulation, and the configuration of thesystem parameters is confirmed, and then the programming implementation of the systemis completed. What’s more, time and frequency domain analysis are presented based onthe complete verification platform. The software and hardware simulation, the FPGA chiptest and the baseband signal analysis have been completed. Results show that our systemdesign is completely correct. At last, all the designs have been implemented on CycloneIV EP4CE115F29C8hardware platform.This article firstly carries on the design of theory algorithm and simulates the designusing Matlab software. And then we can design the framework and realization algorithmbased on FPGA. Now we can use Matlab software to do fixed-point simulation to identifyeach module. Further, we can program using Verilog HDL language. Finally, all the designare implemented on FPGA chips.