Design And Implementation Of Channelization Architecture For Software Defined Radio Based On TPFT

Software defined radio(SDR)has been widely applied to many fields,such as communication,radar,electronic warfare,and instrumentation.The core idea of SDR is to move the analog-to-digital converters(ADCs)and digital-to-analog converters(DACs)as close as possible to the antenna,and to process the digitized data by software or programmable technique.The development of ADC,DAC and digital hardware has greatly promoted the progress of SDR.Many seminal ideas,such as direct RF sampling receiver,can now be realized for contemporary radio communication,demonstrating the tremendous capabilities of SDR.A key component in SDR systems is a real-time configurable digital channelization.For digital channelization,it is generally difficult to obtain a perfect solution that balances all the targets,such as performance,complexity,resource sharing.The design and implementation of channelization are affected by many parameters,such as sampling rate,bandwidth,channel number,frequency resolution,and dynamic configuration.Exploring resource/performance trade-offs for digital channelization has been a matter of concern.Digital channelization is generally implemented by using the following methods:multi-channel digital down conversion(DDC),FFT,polyphase DFT filter bank,tree-structured filter bank,non-uniform filter bank,and analysis/synthesis filter bank,etc.This paper presents a flexible software defined radio channelization architecture that can process two channels of complex input data and provide 1024 independent channels of complex down-converted output data.Parameters of each output channel can be dynamically changed even at run-time in terms of the bandwidth,centre frequency,sampling rate,filter response and gain.The proposed architecture,which consists of a tunable pipelined frequency transform based coarse channelization,can be implemented in a single field programmable gate array(FPGA),providing the flexibility associated with existing ASICs and FPGA cores,but with greater resource efficiency.