Design Of Bayer Image Interpolation Module Of Visual Presenter Based On FPGA

In recent years, visual presenter has been more and more widely applied and played an important role in people’s Daily work, especially in some meetings, exhibitions and teaching. Based on photoelectric conversion technology, it can show the information such as documents, material or process into video signal to output on the projectors and other display equipment. In the image acquisition section of the visual presenter, the original image based on bayer template is acquired by image sensor and the image information loss is serious. But according to customer’ need, a variety of formats signals need to be output in the image display section and on this basis to achieve various functions, so we must recover the lost information. In the current visual presenter design, this process is achieved by using a dedicated DSP chip, which causes not only high cost and the core algorihm of the chip is mastered in some development countries, but also the algorithm cannot fully meet the specific applications of visual presenter. As a result, designing some good algorithm and making it realized on hardware platform and special IC chip finally, have great significance and commercial value for visual presenter manufacturers.In this paper’s design, it adopts the CMOS image sensor manufactured based on bayer template, to capture image signals and deals with the output bayer image signals according to the gradient correlation algorithm, finally outputs the full-color image on digital display devices and finishes the bayer image interpolation design of visual presenter based on FPGA.This paper is mainly about bayer image, captured by1.3megapixel color CMOS image sensor of Micron, is dealed with based on gradient correlation algorithm on FPGA, and then the full color image is shown on minitor, the bayer image interpolation module on FPGA is completed. This system has three features:first, the FPGA control center controls CMOS to output bayer image through I2C bus and the full-color image, obtained after interpolated, is output by DVI interface by1280×1024/60frames resolution to meet the high resolution output requirements. Second, the quality of the reconstructed images is improved significantly after processing based on the gradient correlation algorithm, moreover, the algorithm does not refer to complicated matrix or non-linear operation which is like the traditional iterative and non-iterative method, so it is easy to realize. Lastly, the image storage module is also designed in the back of the image reconstructing module to store images that the users want to save to analyse or other operations. The bayer image is captured by MT9D111Micron image sensor and the FPGA platform is the Virtex-5chip of Xilinx.The system mainly consists of four parts:the bayer image-collecting module, bayer image reconstruction module, image output module and image storage module. When the work mode of image sensor initialized by I2C bus is bypass, bayer image is output to meet the requirements of the system. With the ISE10.1software and each module is designed by using Verilog language and completed in ISE10.1development environment.Finally, the recovered full-color image whose SNR is high to37.46are analysed and the subjective quality is also high. Therefore, the system is able to achieve the bayer image interpolation and can be used in the design of visual presenter based on FPGA, with an extensive practical value.