| With the development of satellite communications, mobile communications,television broadcasting, radar, electronic warfare systems, digital receiver has beenwidely used, therefore a higher demand are put forward on the performance of thedigital receiver. The purpose of this project is to design a test system which can test theperformance parameters of the ADC sampling circuit in digital receiver. The content ofthis paper is to design and realize the test system’s hardware platform, which canreceive the ADC sampling data by optical interface, then store massive data andtransmit these data to computer for ADC performance test.First of all, this paper describes the development of the key technologies in thehardward platform such as the CPCI bus transmission techonology and optical fibertransmission techonology. At the same time this paper also describes the basic functionsof the system and test indicators.Secondly, this paper describes the design of the system’s hardware platform. Fourfibre channel are used to achieve high-speed data reception,in which two channels aresingle-mode and the other two are multi-mode. Every channlel data rate is up to2.5Gbps.Two DDR2memory chip are selected to store the massive fiber data and themaximum storage capacity is2Gb. Using the CPCI bus technology to achieve the datacommunication between the hardware platform and the computer. At the same time ahigh-performance FPGA which includes multi-channel high-speed transceivers is usedin the design. High-speed transceiver can deserialize the high-speed serial data to thelow-speed parallel data which is easy to store in DDR2.Then, this paper decribes the system’s FPGA logic design.The system’s FPGAlogic design includes various functional modules such as the CPCI bus control, DDR2,high-speed transceiver, receive data calibration unit, data unpaking unit and so on.Finally, hardware debugging is given out for modules and the system. Thedebugging results show that system basically meets project requirements. |
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