Research On Digitale Predistortion Of RF Power Amplifier

The significance of the power amplifier (PA) linearization techniques in modernmobile communication is introduced. The discussion on the digital predistortion (DPD)of wireless digital radio frequency transmitter system is expanded from theaforementioned point. Moreover, a description of the basic characteristics ontransmission signal and PA is given. PA modeling and its characteristics are analyzed.In addition, DPD module design and system simulation based on RLS algorithm arecompleted. The result indicates that the improvement of adjacent channel power ratio(ACPR) of the memory polynomial (MP) model can be up to27.3dB.For the deterioration of DPD performance due to high peak to average powerratio (PAPR) of the transmission signal, a new cascaded noise filter crest factor (CF)reduction algorithm is proposed. When it reduces CF of a single-carrier WCDMAsignal, its PAPR is decreased to7.1dB from11.8dB. The final test shows it improvesDPD performance effectively.For reducing the difficulty of hardware realization, the thesis focuses on thealgorithm of loop delay estimation. It includes the intergral part and the fractional one,which are realized by amplitude difference summation and FIR interpolation. Theirarithmetic speed is fast for the FPGA parallel computation. The QRD-RLS algorithm isrealized bysystolic structure for the adaptive algorithm in FPGA, which is an ingeniousapplication of space-for-time hardware implementations.Two kinds of test platforms, the off-line test and hardware one, are presented fordesign scheme in the thesis, and the performance of MP DPD system combined withthe CFR technique is displayed by the result. For the single-carrier WCDMA signal,results of two test show the maximum ACPR improvement of PA outputs are13.8dBand10.9dB respectively; hardware test results show that the optimal improvement ofthird-order intermodulation distortion (IMD3) is29.1dB for the two-tone signal.