Design And Verification Of Video Processing Module Based On FPGA And Dual DSP Structure

With the advent of the digital information age, the digital video image processingtechnology gets a rapid development. The demonds of modern digital video imgaeprocessing algorithms, such as high complexity, high resolution, high real-time, etc,bring acid test to traditional video image processing module.The traditional video image processing module has its own disadvantages due tothe fact that it mainly depends on special Image Capture Card and Image ProcessingCard, and implements its functions by using a PC. Besides being bulky and functioningunitarily, the traditional platform weakens itself for high power consumption as well asits considerable limited processing speed and data size. All those weak points haveimposed restrictions on the practical applications, and as a result, blocked the blossomof those related fields to some extent. At the same time, with the rapid development ofFPGA and DSP technologies, the computing capability is becoming increasinglystronger, which makes the technologies of FPGA and DSP have been extensivelyapplied both militarily and residentially, from national defense to daily production andliving.The main purpose of this dissertation is to design a universal high-speed real-timevideo image processing module based on RapidIO transport protocols, which the FPGAworks as the logical controlling and DSP works as the kernel processor. This module ismainly used to verify and analysis the digital video image processing algorithms, andmeet the modern video image processing’s demands of the rate, the amount of data andpower consumption, and has specific input/output interface. Besides it features real-timeand miniaturization.At the outset, the research background and significance as well as the structures ofthe dissertation is presented, followed by the requirements associated with our design.Then, the general framework of the hardware circuit is put forward according to thedesign requirements. Next, the design of the hardware circuit will be interpreted indetail, including the design of power supply, video data cache unit, various interfacecircuits, video data transfer channel between master cpu and slave cpu, etc. After this, the Open-Operation, the Edge-Detection and the H.264encoder are introduced, and howthese arithmetics are realized in the platform is also shown in the dissertation. At last,the dissertation gives some verification results of the platform and summarizes the totaldesign as well as raises some exploration points for the future research.According to the analysis of the verification results, the platform can worknormally as the video image processing platform. All of the hardware circuits meet thedesign requirements. The video data cache unit of FPGA and DSP can accomplish thedata caching under the400MHz data frequency, the RapidIO communication of FPGAand DSP can work well at3.125Gbit/s, and the general video processing arithmetics canbe transplanted to the platform easily and get the correct test results.