Embedded High Performance RapidIO Bus Digital Modeling Research And Implementation

With the gradual rise in demand for high performance computing in various fields,high performance computing is rapidly moving into the next phase.A single multi-core SOC device has long been unable to meet computing needs.Virtualization technology and highly integrated SOC devices offer the possibility for high-performance computing,which will eventually evolve into tightly coupled clusters of processors for joint computing.These processor clusters will consist of thousands of multi-core SOC devices,and for this architecture,the more efficient the interconnection,the better the performance and economy for the system.Therefore,it is important to find an interconnection technology that supports direct high-speed interconnection between processors,and RapidIO bus technology,as an embedded high-performance interconnection technology,can not only realize direct interconnection between processors but also has the advantages of high reliability,low latency,high speed and high bandwidth.But the traditional embedded development technology can not cope with the development demand of such a large-scale embedded system device,the emergence of digital model simulation technology makes this kind of embedded device development method possible.The research of this thesis focuses on the RapidIO bus model,and the digital modeling of RapidIO bus is realized by using QEMU digital model simulation technology.The final built RapidIO bus digital model is functionally complete,and different RapidIO interconnection system structures can be realized by flexible planning of the switching model.The constructed RapidIO interconnection system will encounter QOS(Quality Of Service)problem in network transmission,and a RapidIO routing algorithm is proposed for the QOS problem existing in RapidIO network.The algorithm can not only obtain routing paths efficiently,but also is more suitable for large-scale RapidIO routing networks.This paper is oriented to the research and implementation of the digital model of RapidIO bus,and the main research contents and the key problems solved are as follows:First,we study the RapidIO protocol and QEMU digital modeling techniques,analyze the specific functions and specifications of the RapidIO three-layer protocol,and perform module design and implementation of the RapidIO bus through QEMU modeling features.Secondly,a RapidIO routing algorithm,MOARR algorithm,is designed based on multi-objective optimization algorithm for QOS problem in RapidIO network transmission.The three target parameters of network packet loss rate,delay,and cost are compared and verified with other algorithms,and the target parameters are overall better than the comparison algorithms.Third,for the node interconnection and mounting problems in the digital model of RapidIO bus,this paper proposes a memory-sharing and memory-moving interconnection strategy,and implements a minimal system for mounting switching nodes and flexibly building routing networks.Finally,based on the RapidIO bus digital model implemented in this paper,the RapidIO interconnection system is constructed,and the verification of the RapidIO bus digital model is completed by using relevant verification tools and the MOARR algorithm proposed in this paper.