Digital Signal Processing On Wireless Communication Oriented Microprocessor Design

With the more and more serious complexity of the communication system, theability of the digital signal processing platform has encountered rigorous requirement onprocessing speed and updating ability. The processing infrastructure consisting ofFPGAs array takes the place of traditional infrastructure consisting of ASICs array tobecome the high-performance processing platform. This platform has got a greatadvantage on re-configurability, upgradability, and processing speed. On this platform,we can adopt two methods, processor mode and logic mode, to realize the algorithm.The processor mode shows great advantages on upgradability, while disadvantage onprocessing speed. In this thesis, we adopt a combined processing mode with processorand accelerators, which has got both the advantage of the two modes above, to achievebetter performance. In the current embedded processor applications, ARM and TI DSPshow great advantages on some computing applications and are widely used in thedigital signal processing on communication field. But in some particular signalprocessing applications, a processor with specific circuits is needed.This thesis designs a microprocessor, which is suitable to the particular applicationon wireless communication digital signal processing. With the deep understanding onthe algorithm, we expand the instruction set from the RISC architecture. Somearithmetic instructions, such as MAC and REV, are added in this architecture to achievea better performance on this specific processing application. In the aspect of the designmethodology, EDA tool is adopted to decrease the design period. A language forinstruction set architecture is used to describe the architecture, which focuses on thearchitecture and instruction set instead of coding and debugging. Meanwhile, this studyconfigures the EDA tool to generate the compiler, which decreases the design period fora compiler, and improve the usability of the processor.This microprocessor has a six-stage pipeline architecture, which consists ofInstruction PreFetch, Instruction Fetch, Instruction Decode, Instruction Execution,Memory Access and Register Writeback. This pipeline architecture can process aninstruction every single cycle, which makes the processor get a good instruction throughput. Meanwhile, with the basis of deep study on the pipeline, we found andsolved the data collision and the branch hazard, which improves the processorperformance. Besides, interrupt is supported to exchange some information withaccelerators, which improve the processing performance further. In the end, we get theRTL code with the software via the architecture description and generate the circuits toverify the design on FPGA.