Design And Implementation Of LTE Uplink Based On Multi-core DSP

LTE-A, the fourth generation mobile communication system, has put forward peakrates where the rate of downlink is1Gbps and that of uplink is500Mbps, which requirethe processor to have a higher processing capacity. However, the existing single-coreprocessor architecture faces the following problems:(1) It is difficult to raise the frequency of single-core processor due to theconstraints in materials, manufacturing and thermal design.(2) The delay of serial signal processing cannot meet the low latency and highthroughput requirements of the next generation of wireless communicationsystem.In response to the problems mentioned above, this article designs and implementsthe parallel Turbo receiver of LTE uplink based on multi-core DSP platform. Signalprocessing based on multi-core platform has the following advantages: multi-coreprocessor improves the processing capacity by increasing the number of processors soas to avoid the "side effects" caused by higher frequency; Parallel signal processing canreduce processing delays and improve data rates. Based on a multi-core DSP platform,this paper completes the following work:First, the selective spanning with fast enumeration algorithm has been improved.The enumerated point will overflow when symbol to be tested is located at the edge ofthe constellation diagram using fast enumeration algorithm. To solve this problem, wepropose an improved fast enumeration algorithm, called New Selective Spanning withFast Enumeration, which does not increase the computational complexity. In the3×3MIMO-OFDM system, when the bit error rate is102,(1) If parameter is4,4,1, the performance of NSSFE algorithm is3dB betterthan original algorithm. The amount of computations was only0.4%of themaximum likelihood detection algorithm with only1dB performance loss.(2) If parameter is8,4,1, the performance of NSSFE algorithm is0.7dB betterthan original algorithm. The amount of computations was only0.8%of themaximum likelihood detection algorithm with only0.25dB performance loss.Second, a parallel solution for quadratic permutation polynomial interleaver isproposed. To meet the needs of high-speed parallel Turbo decoder in LTE system, theinterleaved block number and the address within the block are calculated directly in thismethod. PC203multi-core DSP platform is used to calculate the6144length Turbointerleaving parameters. Test results show that: the speedup ratio is14.39when12DSPcores work in parallel; if20DSP cores work together, the parallel speedup ratio canreach19.93.Third, it designs and implements LTE uplink1×2and2×2receiver links on the multi-core DSP platform. According to the design requirements, multicore DSPplatform’s resources, and simulation results on Matlab platform, the detection scheme isselected. Then the receiver chain is divided into functional units whose communicationspeeds have been determined according to the data rates. At last, code writing and linkdebugging are completed on the PC203multi-core DSP platform.Last, block error rate and delay of the receiver have been tested and analyzed. Thetest results showed that: if the block error rate is0.1, after one parallel interferencecancellation iterative, compared to the Matlab floating-point simulation, performance of1×2link will lose0.1dB, performance of2×2link will lose0.9dB. The total latency ofreceiver is0.26ms, and the processing delay of the key modules meets the designrequirements.The proposed parallelization scheme has the advantage of low latency, high speedand ease to implement, on which relevant research results can be widely used inhigh-speed communication system. This paper enriches the implementation ofnext-generation wireless communication system and provides reference data for parallelsignal processing in communication system.