Study And Implement Of Low-complexity And Multi-rate LDPC Dccodcr

As LDPC codes are widely used in various communications protocol standards, moreand more handsets are in the need to use the LDPC decoder. The handheld device’scharacteristics raise a claim that the LDPC decoder should possess the characteristics of lowcomplexity and compatible with multi-rate. Based on the study and analysis of the presentresearch on LDPC decoding algorithm and implementation of LDPC decoder, the paperfocuses on the challenges that implementation complexity, area and power consumption arevery high because of the large amount of storage resources in LDPC. Taking the LDPC codein CMMB system for example, the paper researches the decoding algorithm, the decoderhardware architecture, information processing unit and so on, two kinds of low complexityLDPC decoder that support double rate of LDPC coder in CMMB system are designed. Themain work was summarized as follow:1) Base of the adaptive linear programming decoding algorithm, the thesis proposes animproved adaptive linear programming decoding algorithm, including the more efficientobjective function, the more simplified constraint conditions and the adoption of moreefficient terminate iteration strategy, to make the LDPC more efficient.2) A low complexity double-rate CMMB-LDPC decoder is designed using thelayered-normalized min-sum decoding algorithm and the compression storage strategy ofcheck node information. After the simulation of RTL level and gate level using the Modelsimtool and the prototype verification using the Altera Stratix II series EP2S180FPGA platform,the proposed LDPC decoder is implemented using SMIC0.18um1P6M CMOS technologywith the core area of4.1*4.1mm2and the storage resources of196.5K bits. The test rusultsshow that the proposed LDPC decoder can achieve the required highest throughput of CMMBstandard, which is10.852Mbps in1/2rate and16.243Mbps in3/4rate, while the decoderworks in55.5MHz. While the decoder’s work frequency up to143MHz, the LDPC decodercan achieve the maximum throughput of34.1Mbps. The typical kernel power consumption is62.5mW which was tested in the system clock frequency of62.5MHz.3) Base of the layered-normalized min-sum decoding algorithm, the paper proposes aniteration parallel method which eliminates the variable node information using the iterationunrolling. Based on the proposed iteration parallel method, a novel Check Node Self-updateDecoding Algorithm is proposed, which can significantly reduce storage resources needed forLDPC decoder while keeping the advantage of excellent decoding error performance and fastconvergence speed as the layerd decoding algorithm. Using the Check Node Self-update Decoding Algorithm, another kind of double-rate CMMB-LDPC decoder is proposed. Theproposed decoder only needs157.5K bits memory resource, which reduces by about20%compared to the LDPC decoder using layered-normalized min-sum decoding algorithm. Asfar as we know, the amount of required memory resources of the proposed LDPC decoder isthe minimum compared to other reported CMMB-LDPC decoders.