Research On TSVs Test In3D-SICs

Along with the shrinking of the transistor nanometer level, the integration of the chip inside is getting higher and higher, and the geometric dimensions of the devices are getting smaller and smaller. Reducing the transistor process dimension and shortening the length of the line in the chip connected to each other become more and more difficult. The cost of new technology is rising steadily,while the profits are gradually reduced. In order to continue to keep Moore’s Law, to get rid of the physical and electrical constraints in IC development process, a new design and manufacturing methods are presented. In this case,three-dimensional stacked integrated circuits(3D-SICs) rise in response to the proper time and conditions. This technique provides a new approach to solve these difficulties.3D chip manufacturing is different from the traditional2D chip manufacturing process,3D-SICs are based on Through-Silicon Vias(TSVs),which allow many dies stacked in the vertical direction to achieve communication. Reducing the feature size of the chip and improving the performance of the chip can be obtained by means of this technology.3D-SICs have many advantages,the shorter interconnect lines between chips,the chip feature size is smaller,the packaging density is greater,larger bandwidth.lower power consumption and higher performance, etc. However,there are many challenges,such as manufacturing process,yield improvement,thermal management,standards development and chip testing and other issues. In order to reduce cost and ensure function normally, in many of these challenges, the chip testing is seriously important.3D-SICs mainly use TSVs to interconnect the chip,while TSVs may lead to defects during the binding process, which make the chip can not communicate, and thus the circuit can not work properly.In response to these issues,this dissertation proposed test method for TSVs during post-bond. Combining with the current3D chip testing method uses the irreversibility of the signal in the conductor transmission, which applied in the transmission end of the test architecture with two different test vectors.Rebounding module located in the other layers receives and rebounds test signal,and we proposed the testing method based on rebound model architecture. The test method can achieve smaller area,shorter time overhead and lower power consumption compared with the other method. In180nm CMOS process, the experimental results show that the test architecture area and the test average power consumption decreased by59.8%and18.4%compared with the other method, and this architecture only need12test clock cycle.