Design And Implementation Of Reconifgurable Parallel Processing Unit In Heterogeneous Multi-Core SoC

With the rapid development of semiconductor manufacturing technology, thenumber of transistors intergrated on a chip increases dramaticly. Traditional systemarchitecture can not meet the demand of billion-transistor area, multi-core SoCemerges and has been widely acknowleged. The heterogeneous multi-core chipintegrated with reconfigurable computing unit is an important branch of multi-corechips. Reconfigurable technology has the advandage of both processors and ASICs,greatly alleviate the contradiction between the performance and flexibility. In faceof new requirements put by high-density computing applications, reconfigurabletechnology has become an important mean. Meanwhile, Network-on-chip isconsidered to be the optimum scheme of on-chip-interconnection. Aiming at signalprocessing algorithms properties that computing process, this dissertation can becategorized into limited types of rules floating-point matrix. Design and implementa reconfigurable parallel processing unit (RCU) based-on the heterogenousmulti-core Soc system of research group, which reached the balance between theadaptive of the hardware algorithm and the execution efficiency of algorithm.Design through the simulation of the modules and reconfiguration units to therealization of the function algorithm, demonstrate its accuracy and the adaptabilityof the algorithm. The main job of this dissertation is as follows:First, analyzed the project team of heterogeneous multi-core SoC systemstructure, put forward the architecture of reconfigurable parallel processing unit(RCU), and explain the characteristics and working principle.Second, implement reconfigurable parallel processing unit in RTL design, giveeach module design idea, the structure of the circuit and the implementation method,and makes detailed analysis of configuration information structure andreconfigurable pattern.Finally, verify the correctness by the simulation each module of reconfigurableparallel processing unit, build a heterogeneous multi-core test system, therealization of plural matrix addition, plural matrix scalar-multiplication andcovariance matrix operation.