Research And Implementation Of Frequency Synthesizer Based On DDS And PLL Technology

Firstly, both advantage and disadvantage of the direct digital and phase-locked loop technologies are introduced and analyzed in the thesis. Due to the two characteristics of narrow band filter and the negative feedback of the phase-locked loop, the frequency synthesizer is able to achieve high frequency stability, good the spectrum purity, smaller frequency step and wider output bandwidth by the methods of fraction-N divider phase-locked loop and multiple PLLs. However, the spur and the loop filter bandwidth of fraction-N divider phase-locked loop limit the frequency resolution and the speed of scanning of the frequency synthesizer. Though the frequency resolution and the frequency scanning speed of DDS is high, its output frequency, with a lot of spur, is low. In order to achieve better frequency synthesizer, a new technology of combining DDS and PLL and three methods of combining DDS and PLL, namely DDS and PLL mixing, DDS being the reference frequency of PLL, DDS in the negative feedback of PLL are introduced and all their functions are analyzed and compared in the thesis.Secondly, according to the different indexes and requirements of two systems, with the aim of doing researching on DDS being the reference frequency of PLL and DDS in the negative feedback of PLL, the scanning frequency synthesizer (the output frequency range from3.976GHz to6.976GHz) which selects the method of DDS as the reference frequency of PLL and the frequency synthesizer (the output frequency range from3GHz to lOGHz, frequency resolution as1Hz) which selects the method of DDS in the negative feedback of PLL are achieved respectively, at the same time, the selection of the key components and the design of the key circuits as well as process of the control program are introduced in detail. Getting rid of strict requirement of the bandwidth of the loop filter from fraction-N divider phase-locked loop, taking the output of DDS as the reference frequency of PLL, the speed of seltting of DDS being the reference frequency of PLL is improved by changing the output after changing the output of DDS and the system resolution is decided by DDS. Putting DDS into the feedback of PLL, DDS in the feedback of PLL works as the divider taking place of fraction-N, the spur of the system can be improved greatly without any modulation.Finally, the results indicate that both these two plans can realize the two different systems mentioned above and the performance of the system. Compared with DDS being the reference frequency of PLL, it is more complex for DDS in the feedback of PLL to achieve sweep with fixed step. However, the DDS being the reference frequency of PLL has a less strict the bandwidth of the output than that of DDS in the feedback of PLL.