Low Power Circuits Design Based On Residue Number System

In recent decades, digital products become smaller, faster and newer rapidly withthe shrinking of semiconductor process geometries and rising of integration density.More and more circuits are integrated into a single chip, power consumption hasbecome one of the bottleneck for integration circuit applications. Thus, lower powertechnology has become one of the key issues for digital systems. At the same time,according to Moore’s Law, IC industry is close the physical limitation So the gap forlow power consumption based on the size of semiconductor is also limited. On the otherhand, the noise can cause seriously performance degrade for deep sub-micrometercircuits. Therefore，the new low power consumption technology of integrated circuitshas become the focus of the current studies.The power dissipation of digital IC is proportional to square of the supply voltage.Therefore, the most direct way to reduce power consumption is to reduce the supplyvoltage. Since both static power and dynamic power consumption are proportional tothe square of the voltage, voltage scaling （VOS）^[1]-[2]has been widely used as aneffective method to reduce power consumption. With the characteristic size of CMOSdevices reaching nano-scale, the effect of Deep Submicron （DSM） noise, which iscaused by supply voltage reduction, will become an irresistible obstacle for the reliablecomputation. To avoid the losing of computing performance, shorten the critical path ofthe circuit is an effective method. It could be the guideline for high performance andlower power consumption circuit design.Based on the above ideas, this thesis reviews the Residue Number System （RNS）in detail, which is a different number system compared with Binary Number System. Inthe RNS, the long critical path in traditional binary number system is split into severalshorter parallel paths in RNS. The critical path can reduced greatly. So the circuit canstill work properly in the case of voltage reduction and the power consumptiondecreases without computation performance sacrifice. The hardware structures of1024point FFT are designed and realized in RNS domain, and their corresponding powerconsumption models and error probability models are implemented on DC and Hspice. Compared with theoretical results, the feasibility of VOS in RNS domain is verified andimproved. In order to further improve the feasibility and practicality of the RNS, wepropose Reduced Precision Redundancy （RPR） based scaling scheme for RNS. Withthis new technology, we design high efficient256-state Viterbi decoder,48-tap FIRfilter, and a16-point FFT arithmetic circuit. According simulation results, we find thatthe algorithm structure based on the RPR-RNS outperforms the traditional RNSalgorithm in some application conditions.