The Design And Implementation Of Detection Unit And Operation Unit In Residue Number System

With the rapid development of integrated circuit industry, the performance requirements of the chip have become more higher and higher, the traditional parallel technology has been unable to meet the design requirement for high performance,so need to introduce such as the remainder system truly parallel processing of numerical representation system.In RNS,independent and parallel of each channel and the characteristic of avoid carry transmission,make it has a great application value in the field of high speed digital processing,so the study of remainder system related problem is very meaningful.This thesis mainly is to research detection problem and modular multipler,it’s the main work content is as follows:.1、 Compared to traditional parity detection algorithm proposed three modular {2_n+1，2_n-1,2_2n+1} improved algorithm,and completed the VLSI circuit implementation of corresponding algorithm. Among them, the parity detection algorithm in this paper relative to the previous algorithm, its advantage lies in the algorithm to eliminate the division operation and the use of table lookup, only using one moduli adder, a comparator, a multiplexer and some simple combinational logic circuit implementation, simplifying the complexity of the design.2、 Compared to traditional symbol detection algorithm proposed four modular {2_n+1，2_n-1,2_2n+1} improved algorithm, and completed the VLSI circuit implementation of corresponding algorithm. Among them,the symbol detection algorithm in this paper relative to the previous algorithm,its advantage lies in reduced the number of modular arithmetic unit, but also do not need to introduce redundant remainder, only through the use of a n bit moduli adder with some of the common binary adder and combinational logic unit, simplifies the structure of the circuit.3、 Proposed a new algorithm of 2 5n± modular multiplier, then completed the VLSI circuit implementation of corresponding algorithm. Among them, the 2 +5nmodular multiplier algorithm completely eliminate the moduli operation, its operation results are obtained only by an ordinary binary addercalculation,greatly simplifies the complexity of the circuit; The advantage of 2-5nmodular multiplier algorithm lies in reducing modular adder unit operating digital wide.